A Type I PLL incorporates a VCO with $K_o=100 \mathrm{MHz} / \mathrm{V}$, a phase detector with $K_d=1 \mathrm{~V} / \mathrm{rad}$, and a first-order, lowpass filter with $\omega_{L P F}=2 \pi \times 10^6$ radians/s shown below. A divider of 100 has been placed in the feedback path to implement a frequency synthesizer.  (b.) If a step input of $\Delta \phi_{\text {in }}$ is applied at $t=0$, what is the steadystate phase error at the output of the phase detector, $\phi_e$ ? The steady-state error is evaluated by multiplying the desired phase by $s$ and letting $s \rightarrow 0$.